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02011-DSH-001-C mindspeed technologies ? april 2007 preliminary information/mindspeed proprietary and confidential m02011 cmos transimpedance amplifier with agc for fiber optic networks up to 622 mbps applications apon bpon atm/sonet the m02011 is a cmos transimpedance amplifier with ag c. the agc gives a wide dynamic range of 40 db. the high transimpedance gain of 66 k ? ensures good sensitivity. for optimum system performance, the m02011 die should be mounted with a gaas or ingaas pin photodetector inside a lensed to-can or other optical sub-assembly. the m02011 can either bias the pin diode from the internal regulator, or use an externally biased pin diode. a replica of the average photodiode current is available at the mon pad for photo-alignment and 'loss of signal' monitoring. features typical -34 dbm sensitivity, +6 dbm saturation at 622 mb/s when used with 0.9 a/w ingaas pin. (cpd 0.5 pf, ber 10 -10 ) typical differential transimpedance: 65 k ? fabricated in standard cmos differential output standard +3.3 volt supply available in die form only monitor output agc provides dynamic range of 40 db internal or external bias for photodiode pin or apd sensor same pad layout and die size as m02013/14/15/16 typical applications diagram pina dout doutb v cc pink 470 pf 1 nf monitor output rm typically ac-coupled to limiting amplifier limiting amplifier m02011
02011-DSH-001-C mindspeed technologies ? ii preliminary information/mindspeed proprietary and confidential *for full ordering number please contact sales ordering information part number package operating temperature m02011-xx* waffle pack ?40 c to 95 c m02011-xx* expanded whole wafer on a ring ?40 c to 95 c revision history revision level date description c released april 2007 production release. increased max operating temperature, updated specifications based on full device characterization and in cluded information on assembly, i mon and using the device with externally biased detectors in the applications information section. pad configuration mon pina pink v cc agc dout gnd gnd doutgnd 1 2 3 4 56 7 8 9 10 11 12 v cc dout doutgnd die size 1090 x 880 m top level diagram pink mon v cc dout doutb agc gnd pina
02011-DSH-001-C mindspeed technologies ? 1 preliminary information/mindspeed proprietary and confidential 1.0 product specification 1.1 absolute maximum ratings these are the absolute maximum ratings at or beyond which the ic can be expected to fail or be damaged. reli - able operation at these extremes for any length of time is not implied. 1.2 recommended operating conditions table 1-1. absolute maximum ratings symbol parameter rating units v cc power supply (v cc -gnd) -0.4 to +4 v t a operating ambient -40 to +95 c t stg storage temperature -65 to +150 c i in pina input current 8 (1) ma pp v pina , v pink , v dout , v doutb ,v agc , v mon maximum input voltage at pina, pink, dout, doutb, agc and mon -0.4v to vcc + 0.4v v i pink maximum average current sourced out of pink 10 ma i dout , i doutb maximum average current sourced out of dout and doutb 10 ma notes: 1. equivalent to 4.9 ma average curren t with an extinction ratio of 10 db. table 1-2. recommended operating conditions symbol parameter rating units v cc power supply (v cc -gnd) 3.3 10% v c pd max. photodiode capacitance (v r = 1.8 v), for 622 mbps data rate 1.0 pf t a operating ambient temperature -40 to +95 c
product specification 02011-DSH-001-C mindspeed technologies ? 2 preliminary information/mindspeed proprietary and confidential 1.3 dc characteristics 1.4 ac characteristics table 1-3. dc characteristics symbol parameter min. typ. max. units v b photodiode bias voltage (pink - pina) 1.7 2.0 2.2 v v cm common mode output voltage 0.7 1 1.3 v i cc supply current (no loads) 20 28 35 ma r load recommended differential output loading 85 100 (1) ? ? note: 1. 100 ? is the load presented by the limiting amplifier. table 1-4. ac characteristics symbol parameter condition min. typ. (1) max. units r out output impedance (single ended) 30 50 70 ? lfc low frequency cutoff (2) ?1317khz v d differential output voltage 100 ? differential load ? 250 450 mv dcd duty cycle distortion (3) 622 mbps ? ? 80 ps dj deterministic jitter (includes dcd) (3) 622 mbps, 2 23 - 1 prbs ? ? 120 ps pp pdj pattern dependant jitter (at crossing point), with no dcd 622 mbps, 2 23 - 1 prbs ? ? 55 ps pp in, rms total input rms noise dc to 467 mhz (bessel filter), cin = 0.5 pf ?5060na total input rms noise dc to 467 mhz (bessel filter), cin = 1 pf ?5670na pin_mean_min optical sensitivity (4) -33 -34 ? dbm imon_off monitor ou tput offset (5) v mon = 0 to 2v ? ? 1.3 a imon_ratio monitor output gain ratio (5) v mon = 0 to 2v ? 0.7 ? ? imon_error monitor output accuracy (3, 5) v mon = 0 to 2v ? ? 2 db notes: 1. die designed to operate over an ambient temperature range of -40c to +85c, t a and v cc range from 3.0 - 3.6v. ty pical values are tested at t a = 25 c and v cc = 3.3v. 2. input -33 dbm, extinction ratio = 10, temp = 25c. 3. input current < 1 ma average. 4. ber 10 -10 , pd capacitance = 0.5 pf, responsivity 0.9 a/w, extinction ratio = 10, temp = 25c. 5. offset and slope adjustment necessary to achieve rated accuracy.
product specification 02011-DSH-001-C mindspeed technologies ? 3 preliminary information/mindspeed proprietary and confidential 1.5 dynamic characteristics 1.6 typical performance v cc = 3.3v, temperature = 25 c, l in = 1 nh, unless otherwise stated. table 1-5. dynamic characteristics symbol parameter min. typ. max. units g transimpedance - single ended - differential 26.5 53 32.5 65 38 76 k ? bw bandwidth to -3 db point @ -33 dbm, 0.9a/w, 0.5 pf pd 450 600 ? mhz bandwidth to -3 db point @ -33 dbm, 0.9a/w, 1 pf pd ? 460 ? rc agc loop time constant ? 2 ? s i agc agc threshold ? 5 ? a pp i ovl maximum functional input current 3.6 (1) ??ma psrr power supply rejection, f < 1 mhz ? 22 ? db notes: 1. equivalent to +3.4 dbm input optical power at extinction ratio = 10, responsivity = 1.0 a/w. figure 1-1. typical performance diagrams 1 of 3 typical differential transimpedance vs. v agc 0 10 20 30 40 50 60 70 00.511.52 v agc (v) differential transimpedance (k ? )
product specification 02011-DSH-001-C mindspeed technologies ? 4 preliminary information/mindspeed proprietary and confidential v cc = 3.3v, temperature = 25 c, l in = 1 nh, unless otherwise stated. figure 1-2. typical performance diagrams 2 of 3 m02011 bandwidth vs . input capacitance 3.3v, nom, l in = 1nh 400 450 500 550 600 650 700 750 0.2 0.4 0.6 0.8 1 cin (pf) bandwidth (mhz) t = -40oc t = 0oc t = 27oc t = 85oc t = 110oc m02011 bandwidth vs . temperature 3.3v, nom, l in = 1nh 400 450 500 550 600 650 700 750 -40 10 60 110 junction temperature (oc) bandwidth (mhz) cin = 0.3pf cin = 0.5pf cin = 0.75pf cin = 1.0pf -60 -40 -20 0 20 40 60 1 10 100 1000 10000 jitter (ps) pdj ps pp dcd ps dj ps pp m02011 jitter characteristics vs . i in 3.3v, nom, l in = 1 nh, c in = 0.5 pf, 622 mbps (note: dj = pdj + |dcd|) input current ( a pp )
product specification 02011-DSH-001-C mindspeed technologies ? 5 preliminary information/mindspeed proprietary and confidential v cc = 3.3v, temperature = 25 c, l in = 1 nh, unless otherwise stated. figure 1-3. typical performance diagrams 3 of 3 m02011 imon characteristics after calibration 0 200 400 600 800 1000 1200 1400 1600 0 200 400 600 800 1000 1200 1400 input current (ua) imon current (ua) m02011 imon error after calibration -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 0 1 10 100 1000 10000 input current (ua) imon error (db optical)
02011-DSH-001-C mindspeed technologies ? 6 preliminary information/mindspeed proprietary and confidential 2.0 pin definitions table 2-1. pad description die pad no name function 1 agc monitor or force agc voltage 2v cc power pin. connect to most positive supply 3 pink common pin input. connect photo diode cath ode here and a 470 pf capacitor to gnd (1) 4 pina active pin input. connect to photo diode anode 5v cc power pin. connect to most positive supply (only one v cc pad needs to be connected) 6 mon analog current source output. current matched to average photodiode current 7 dout differential data outp ut (goes low as light increases) 8dout gnd ground return for dout pad (2) 9 gnd ground pin. connect to the most negative supply (2) 10 gnd ground pin. connect to the most negative supply (2) 11 doutgnd ground return for dout pad (2) 12 dout differential data outp ut (goes high as light increases) na backside backside. connect to the lowest potential, usually ground notes: 1. alternatively the photodiode cathode may be connected to a decoupled positive supply, e.g. v cc . 2. all ground pads are common on the die. only one ground pad needs to be connected to the to-can ground. however, connecting mo re than one ground pad to the to-can ground, particularly those across the die from each other can improve performance in noisy environ ments. figure 2-1. bare die layout mon pina pink v cc agc dout gnd gnd doutgnd 1 2 3 4 56 7 8 9 10 11 12 v cc dout doutgnd
02011-DSH-001-C mindspeed technologies ? 7 preliminary information/mindspeed proprietary and confidential 3.0 functional description 3.1 overview the m02011 is a cmos transimpedance amplifier with agc. the agc gives a wide dynamic range of 40 db. the high transimpedance gain of 66 k ? ensures good sensitivity. for optimum system performance, the m02011 die should be mounted with a gaas or ingaas pin photodetector inside a lensed to-can or other optical sub-assembly. the m02011 can either bias the pin diode from the internal regulator, or use an externally biased pin diode. a replica of the average photodiode current is available at the mon pad for photo-alignment and 'loss of signal' (los) monitoring. figure 3-1. m02011 block diagram dc restore phase splitter agc pina pink mon dout dout 2.6 v 1 v dc shift
functional description 02011-DSH-001-C mindspeed technologies ? 8 preliminary information/mindspeed proprietary and confidential 3.2 general description 3.2.1 tia (transimpedance amplifier) the transimpedance amplifier consists of a high gain single-ended cmos amplifier (tia), with a feedback resistor. the feedback creates a virtual earth low impedance at the input and virtually all of the input current passes through the feedback resistor, defining the voltage at the out put. advanced cmos design techniques are employed to maintain the stability of this st age across all input conditions. an on-chip low dropout linear regulator has been incorporated into the design to give excellent noise rejection up to several mhz. higher frequency power supply noise is removed by the external 470 pf decoupling capacitor con - nected to pink. the circuit is designed for pin photodiodes in the ?grounded cathode? configuration, with the anode connected to the input of the tia and the cathode connected to ac ground, such as the provided pink terminal. reverse dc bias is applied to reduce the photodiode capacitance. avalanche photodiodes can be connected externally to a higher voltage. 3.2.2 agc the m02011 has been designed to operate over the input range of +6 dbm to -34 dbm. this represents a ratio of 1:10000 whereas the acceptable dynamic range of the output is only 1:30 which implies a compression of 333:1 in the transimpedance. the design uses a mos transistor operat ing in the triode region as a ?voltage controlled resis - tor? to achieve the transimpedance variation. another feature of the agc is that it only operates on signals greater than -26 dbm (@0.9 a/w). this knee in the gain response is important when setting ?signal detect? functions in the following post amplifier. it also aids in active photodiode alignment. the agc pad allows the agc to be disabled during photodiode alignment by grounding the pad through a low impedance. the agc control voltage can be monitored during normal operation at this pad by a high impedance (>10 m ? ) circuit. 3.2.3 output stage the signal from the tia enters a phase splitter followed by a dc-shift stage and a pair of voltage follower outputs. these are designed to drive a differential (100 ? ) load. they are stable for drivin g capacitive loads, such as inter - stage filters. each output has its own gnd pad, all four gnd pads on the chip should be connected for proper operation. since the m02011 exhibits rapid roll-off (3 pole), simple external filtering is sufficient. 3.2.4 monitor o/p high impedance output sources a replica average photodiode current for monitoring purposes. this output is com - patible with the ddmi receive power specification (sfp-8472) and mindspeed?s range of ddmi controllers. ensure that the voltage on v mon is in the range of 0 to 2v. refer to figure 4-1 .
02011-DSH-001-C mindspeed technologies ? 9 preliminary information/mindspeed proprietary and confidential 4.0 applications information 4.1 recommended pin diode connections figure 4-1. suggested pin diode connection methods recommended circuit pina dout doutb v cc pink 470 pf 1 nf monitor output rm m02011 alternative circuit - cathode connected to v cc pina dout doutb v cc pink 470 pf 1 nf monitor output rm 500 ? 470 pf m02011 note: selection of rm depends on the maximum input current as detailed in ta bl e 4 - 1 .
applications information 02011-DSH-001-C mindspeed technologies ? 10 preliminary information/mindspeed proprietary and confidential 4.2 monitor calibration to achieve the best monitor accuracy, both the slope and ca librated offset should be used. the offset calibration is achieved by measuring the dark current from the mon output. the calibrated monitor value is usually determined by y = mx + b or: i mon_calibrated = (slope * i mon_reading ) + i mon_offset where slope = 1/imon_ratio ( ta b l e 1-4 ) = 1/0.7 = 1.43 and i mon_offset = i input@cal - (i mon_reading@cal * slope) 4.3 selecting the monitor resistor as described earlier the high impedance monitor output sources a replica average photodiode current for monitor - ing purposes. if detected by converting the current to a voltage through an external resistor ( figure 4-1 ), ensure that the voltage on v mon is in the range of 0 to 2v. the table below provides suggested values for the monitor resistor. table 4-1. selection of rm for maximum input current i in max (ma) optical power (dbm) rm ( ? ) 4 +6 500 2 +3 1000 1 0 2000 0.5 -3 4000
applications information 02011-DSH-001-C mindspeed technologies ? 11 preliminary information/mindspeed proprietary and confidential 4.4 to-can layout figure 4-2. typical layout di agram with photodio de mounted on pink capacitor (5 pin tocan) notes: typical application inside of a five lead to-can. only one of the v cc pads and all of the gnd pads need to be connected. the backside must be connected to the lowest potential, usually ground, with conductive epoxy or a similar die attach material. if a monitor output is not required then a four lead to-can may be used. v cc mon dout doutb 1nf 470pf
applications information 02011-DSH-001-C mindspeed technologies ? 12 preliminary information/mindspeed proprietary and confidential 4.5 treatment of pink pink requires bypassing to ground with a capacitor when powering a photo diode. if pink is not used to bias the photo diode, then it is not necessary to bypass an unused pink. figure 4-3. typical layout diagram with photodiode mounted on tocan base (5 pin tocan) notes: typical application inside of a five lead to-can. only one of the v cc pads and all of the gnd pads need to be connected. the backside must be connected to the lowest potential, usually ground, with conductive epoxy or a similar die attach material. if a monitor output is not required then a four lead to-can may be used. v cc mon dout doutb 1nf 470pf
applications information 02011-DSH-001-C mindspeed technologies ? 13 preliminary information/mindspeed proprietary and confidential 4.6 t0-can assembly recommendations 4.6.1 assembly the m02011 is designed to work with a wirebond inductance of 1 nh 0.25 nh. many existing to-can configurations will not allow wirebond lengths that short, since the pin di ode submount a nd the tia di e are more than 1 mm away in the vertical direction, due to the need to have the pin diode in the correct focal plane. this can be remedied by raising up the tia di e with a conductive metal shim. this will effectively reduce the bond wire length. refer to figure 4-4 above for details. figure 4-4. to-can assembly diagram m02015 ceramic shim submount to can leads (x 4or 5) pin diode wire bond to-can header m02015 ceramic shim submount to can leads (x 4or 5) pin diode wire bond to-can header not recommended example recommended example capacitor 470 pf 470 pf capacitor metal shim
applications information 02011-DSH-001-C mindspeed technologies ? 14 preliminary information/mindspeed proprietary and confidential mindspeed recommends ball bonding with a 1 mil (25.4 m) gold wire. for performance reasons the pina pad is smaller than the others and also has less via material connected to it. it therefore requires more care in setting of the bonding parameters. for the same reason pina has no esd protection. in addition, please refer to the mindspeed product bulletin (document number 0201x-pbd-002). care must be taken when selecting chip capacitors, since they must have good low esr characteristics up to 1.0 ghz. it is also important that the termination materials of the capacitor be compatible with the attach method used. for example, tin/lead (pb/sn) solder finish capacitors are incompatible with silver-filled epoxies. palladium/silver (pd/ag) terminations are compat ible with silver filled epoxies. solder can be used only if the substrate thick-film inks are compatible with pb/sn solders. 4.6.2 recommended assembly procedures for esd protection the following steps are recommended for to-can assembly: a. ensure good humidity control in the environment (to help minimize esd). b. consider using additional ionization of the air (also helps minimize esd). c. as a minimum, it is best to ensure that the body of the to-can header or the ground lead of the header is grounded through the wire-bonding fixture for the following steps. the wire bonder itself should also be grounded. 1. wire bond the ground pad(s) of the die first. 2. then wire bond the v cc pad to the to-can lead. 3. then wire bond any other pads going to the to-can leads (such as dout, dout and possibly mon) 4. next wire bond any capacitors inside the to-can. 5. inside the to-can, wire bond pink. 6. the final step is to wire bond pina.
applications information 02011-DSH-001-C mindspeed technologies ? 15 preliminary information/mindspeed proprietary and confidential 4.7 tia use with externally biased detectors in some applications, mindspeed tias are used with detectors biased at a voltage greater than available from tia pin cathode supply. this works well if some basic cautions are observed. when turned off, the input to the tia exhibits the following i/v characteristic: in the positive direction after about 700 mv, the impedance of the input is relatively high. after the tia is turned on, the dc servo and agc circuits attempt to null any input currents (up to the absolute maximum stated in ta b l e 1-1 ) as shown by the i/v curve in figure 4-6 . figure 4-5. tia use with externally biased detectors, powered off pina unbiased -300 -250 -200 -150 -100 -50 0 50 100 -800 -600 -400 -200 0 200 400 600 800 1000 1200 mv a
applications information 02011-DSH-001-C mindspeed technologies ? 16 preliminary information/mindspeed proprietary and confidential it can be seen that any negative voltage below 200 mv is nulled and that any positive going voltage above the pina standing voltage is nulled by the dc servo. the dc servo upper bandwidth varies from part to part, but is generally at least 30 khz. when externally biasing a detector such as an apd where the supply voltage of the apd exceeds that for pina ta bl e 1-1 , care should be taken to power up the tia first and to keep the tia powered up until after the power supply voltage of the apd is removed. failure to do this with the tia unpowered may result in damage to the input fet gate at pina. in some cases the damage may be very subtle, in that nearly normal operation may be experienced with the damage causing slight reductions in bandwidth and corresponding reductions in input sensitivity. figure 4-6. tia use with externally biased detectors, powered on pina biased -1000 -800 -600 -400 -200 0 200 400 600 800 1000 -300 -200 -100 0 100 200 300 400 500 600 700 mv a
02011-DSH-001-C mindspeed technologies ? 17 preliminary information/mindspeed proprietary and confidential 5.0 die specification figure 5-1. bare die layout mon pina pink v cc agc dout gnd gnd doutgnd 1 2 3 4 56 7 8 9b 10b 11 12 v cc dout doutgnd 9a 9c 10a 10a pad number pad x y 1 agc -329 -76 2 (1) v cc -329 -228 3 pink -124 -434 4 pina 124 -434 5 (1) v cc 329 -228 6mon 329 -76 7dout 329 76 8 (1) dout gnd 329 228 9c (1, 2) gnd 329 360 9b (1, 2) gnd 255 434 9a (1, 2) gnd 124 434 10a (1, 2) gnd -124 434 10b (1, 2) gnd -255 434 10c (1, 2) gnd -329 360 11 (1) doutgnd -329 228 12 dout -329 76 notes: 1. it is only necessary to bond one v cc pad and one gnd pad. however, bonding one of each pad (if available) on each side of the die is encouraged for improved performance in noisy environ- ments. 2. each location is an ac ceptable bonding location. notes: process technology: cmos, silicon nitride passivation die thickness: 300 m pad metallization: aluminium die size: 880 m x 1090 pad opening: 86 msq. octagonal pad: 70 m across flat pina (70 m x 70 m) pad centers in m referenced to center of device connect backside bias to ground
? 2005 - 2007, mindspeed technologies ? , inc. all rights reserved. information in this document is provided in connection with mindspeed technologies tm ("mindspeed tm ") products. these materials are provided by mindspeed as a service to its customers and may be used for informational purposes only. except as provided in mindspeed?s terms and conditions of sale for such products or in any separate agreement related to this document, mindspeed assumes no liability whatsoev er. mindspeed assumes no responsibility for errors or omission s in these materials. mindspeed may make changes to specifications and product descriptions at any time, without notice. mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities ar ising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. these materials are provided "as is" without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including liability or warranties relating to fitness for a particul ar purpose, consequential or incidental damages, merchantability, or infringement of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text, graph ics or other items contained within these materials. mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including without li mitation, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. mindspeed customers using or selling mindspeed prod ucts for use in such applications do so at their own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale. 02014-dsh-001-a mindspeed technologies ? 18 mindspeed proprietary and confidential
02011-DSH-001-C mindspeed technologies ? 19 preliminary information/mindspeed proprietary and confidential www.mindspeed.com general information: (949) 579-3000 headquarters - newport beach 4000 macarthur blvd., east tower newport beach, ca. 92660

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